february 1999 f dc65 8p single p-channel, logic level, powertrench tm mosfet general description features absolute maximum ratings t a = 25c unless otherwise note symbol parameter ratings units v dss drain-source voltage -30 v v gss gate-source voltage - continuous 20 v i d drain current - continuous (note 1a) -4 a - pulsed -20 p d maximum power dissipation ( note 1a) 1.6 w (note 1b) 0.8 t j ,t stg operating and storage temperature range -55 to 15 0 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 78 c/w r q jc thermal resistance, junction-to-case (note 1) 30 c/w FDC658P rev.c this p -channel logic level mosfet is produced using fairchild semiconductor 's advanced powertrench process that has been especially tailored to minimize the on-state resistance and yet maintain low gate charge for superior switching performance . these devices are well suited for notebook computer applications: load switching and power management, battery charging circuits, and dc/ dc conversion. -4 a, -3 0 v. r ds(on ) = 0.050 w @ v gs = -10 v r ds(on ) = 0.075 w @ v gs = -4 .5 v . low gate charge (8nc typical). high performance trench technology for extremely low r ds(on) . supersot tm -6 package: small footprint (72 % smaller than s tandard so-8); l ow profile (1mm thick). soic-16 sot-23 supersot t m -8 so-8 sot-223 supersot t m -6 d d d s d g supersot -6 tm .658 pin 1 3 5 6 4 1 2 3 ? 1999 fairchild semiconductor corporation
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = -250 a -30 v d bv dss / d t j breakdown voltage temp. coefficient i d = -250 a , referenced to 25 o c -22 mv/ o c i dss zero gate voltage drain current v ds = -24 v , v gs = 0 v -1 a t j = 55 o c -10 a i gssf gate - body leakage, forward v gs = 20 v, v ds = 0 v 100 na i gssr gate - body leakage, reverse v gs = -20 v, v ds = 0 v -100 na on characteristics (note 2) v gs (th) gate threshold voltage v ds = v gs , i d = -250 a -1 -1.7 -3 v d v gs(th) / d t j gate threshold voltage temp.coefficient i d = -250 a , referenced to 25 o c 4.1 mv/ o c r ds(on) static drain-source on-resistance v gs = -10 v, i d = -4 .0 a 0.041 0.05 w t j = 125 o c 0.058 0.08 v gs = -4.5 v, i d = -3.4 a 0.06 0.075 i d (on) on-state drain current v gs = -10 v, v ds = -5 v -20 a g fs forward transconductance v ds = -5 v, i d = -4 a 9 s dynamic characteristics c iss input capacitance v ds = -15 v, v gs = 0 v, 750 pf c oss output capacitance f = 1.0 mhz 220 pf c rss reverse transfer capacitance 100 pf switching ch aracteristics (note 2 ) t d(on ) turn - on delay time v dd = -15 v, i d = -1 a, 12 22 ns t r turn - on rise time v gs = -10 v, r gen = 6 w 14 25 ns t d(off) turn - off delay time 24 38 ns t f turn - off fall time 16 27 ns q g total gate charge v ds = -15 v, i d = -4 .0 a, 8 12 nc q gs gate-source charge v gs = -5 v 1.8 nc q gd gate-drain charge 3 nc drain-source diode characteristics i s continuous source diode current -1.3 a v sd drain-source diode forward voltage v gs = 0 v, i s = -1.3 a (note 2 ) -0.76 -1.2 v notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. a. 78 o c/w when mounted on a 1 in 2 pad of 2oz cu on fr-4 board . b . 156 o c/w when mounted on a minimum pad of 2oz cu o n fr-4 board. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. FDC658P rev.c
FDC658P rev.c 0 1 2 3 4 0 4 8 12 16 20 -v , drain-source voltage (v) - i , drain-source current (a) ds d -4.5v -4.0v -6.0v -3.5v -3.0v v = -10v gs 0 4 8 12 16 20 0.8 1 1.2 1.4 1.6 1.8 2 - i , drain current (a) drain-source on-resistance v = -4.0 v gs d r , normalized ds(on) -10.0v -4.5v -6.0v -8.0v -5.0v typical electrical characteristics figure 1. on-region characteristics . figure 2. on-resistance variation with drain current and gate voltage . figure 3. on-resistance variation with temperature . figure 5. transfer characteristics. 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0.0001 0.001 0.01 0.1 1 10 20 -v , body diode forward voltage (v) -i , reverse drain current (a) 25c -55c v = 0v gs sd s t = 125c j figure 4 . on-resistance variation with gate-t o -source voltage. -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j r , normalized ds(on) v = -10v gs i = -4a d 2 4 6 8 10 0 0.04 0.08 0.12 0.16 -v , gate to source voltage (v) gs r , on-resistance (ohm) ds(on) i = -2a d t = 125c j t = 25c j 1 2 3 4 5 6 0 4 8 12 16 20 -v , gate to source voltage (v) - i , drain current (a) v = -5v ds gs d t = -55c j 125c 25c figure 6 . body diode forward voltage varia tion with source current and temperature.
FDC658P rev.c figure 10 . single pulse maximum power dissipation. 0.1 0.3 1 3 7 15 30 30 100 300 1000 3000 -v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0 v gs c oss c rss figure 8. capacitance characteristics . figure 7 . gate charge characteristics. figure 9. maximum safe operating area. typical electrical characteristics (continued) 0 3 6 9 12 15 0 2 4 6 8 10 q , gate charge (nc) -v , gate-source voltage (v) g gs v = -5v ds -15v i = -4a d -10v 0.1 0.2 0.5 1 2 5 10 20 50 0.01 0.03 0.1 0.3 1 3 10 30 80 -v , drain-source voltage (v) -i , drain current (a) rds(on) limit d ds v = -10v single pulse r = 156c/w t = 25c q ja gs a dc 1s 100ms 10ms 1ms 100us 0.01 0.1 1 10 100 300 0 1 2 3 4 5 single pulse time (sec) power (w) single pulse r =156c/w t = 25c q ja a 0.00001 0.0001 0.001 0.01 0.1 1 10 100 300 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 duty cycle, d = t / t 1 2 r (t) = r(t) * r r = 156c/w t - t = p * r (t) a j p(pk) t 1 t 2 q ja q ja q ja q ja figure 11 . transient thermal response curve . thermal characterization performed using the conditions described in n ote 1b. transient thermal response will change depending on the circuit board design.
? 1998 fairchild semiconductor corporation ssot-6 unit orientation conductive embossed carrier tape f63tnr label customize label antistatic cover tape ssot-6 packaging configuration: figure 1.0 components leader tape 390mm minimum trailer tape 160mm minimum ssot-6 tape leader trailer configuration: figure 2.0 cover tape carrier pin 1 tape note/comments packaging option ssot-6 packaging information standard (no flow code) d87z packaging type reel size tnr 7?dia tnr 13 qty per reel/tube/bag 3,000 10,000 box dimension (mm) 184x187x47 343x343x64 max qty per box 9,000 20,000 weight per unit (gm) 0.0158 0.0158 weight per reel (kg) 0.1440 0.4700 184mm x 184mm x 47mm pizza box for standard option f63tnr label f63tnr label f63tnr label sample 343mm x 342mm x 64mm intermediate box for d87z option 631 631 631 631 lot: cbvk741b019 fsid: fdc633n d/c1: d9842 qty1: spec rev: qarv: spec: qty: 3000 d/c2: qty2: cpn: (f63tnr)2 f63tnr label supersot tm -6 tape and reel data and package dimensions december 1998, rev. b
p1 a0 d1 p0 f w e1 d0 e2 b0 tc wc k0 t dimensions are in inches and millimeters tape size reel option dim a dim b dim c dim d dim n dim w1 dim w2 dim w3 (lsl-usl) 8mm 7?dia 7.00 177.8 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 2.165 55 0.331 +0.059/-0.000 8.4 +1.5/0 0.567 14.4 0.311 ?0.429 7.9 ?10.9 8mm 13?dia 13.00 330 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 4.00 100 0.331 +0.059/-0.000 8.4 +1.5/0 0.567 14.4 0.311 ?0.429 7.9 ?10.9 see detail aa dim a max 13?diameter option 7 diameter option dim a max see detail aa w3 w2 max measured at hub w1 measured at hub dim n dim d min dim c b min detail aa notes: a0, b0, and k0 dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c). 20 deg maximum component rotation 0.5mm maximum 0.5mm maximum sketch c (top view) component lateral movement typical component cavity center line 20 deg maximum typical component center line b0 a0 sketch b (top view) component rotation sketch a (side or front sectional view) component rotation user direction of feed ssot-6 embossed carrier tape configuration: figure 3.0 ssot-6 reel configuration: figure 4.0 dimensions are in millimeter pkg type a0 b0 w d0 d1 e1 e2 f p1 p0 k0 t wc tc ssot-6 (8mm) 3.23 +/-0.10 3.18 +/-0.10 8.0 +/-0.3 1.55 +/-0.05 1.00 +/-0.125 1.75 +/-0.10 6.25 min 3.50 +/-0.05 4.0 +/-0.1 4.0 +/-0.1 1.37 +/-0.10 0.255 +/-0.150 5.2 +/-0.3 0.06 +/-0.02 supersot tm -6 tape and reel data and package dimensions, continued december 1998, rev. b
? 1998 fairchild semiconductor corporation supersot ? -6 (fs pkg code 31, 33) 1 : 1 scale 1:1 on letter size paper dimensions shown below are in: inches [ m ill imeters ] part weight per unit (gram): 0.0158 supersot tm -6 tape and reel data and package dimensions, continued september 1998, rev. a
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